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5895 8-BIT SERIAL-INPUT, LATCHED DRIVERS
Data Sheet 26182.14B*
5895
BiMOS II 8-BIT SERIAL INPUT, LATCHED SOURCE DRIVERS
The UCN5895A, UCN5895EP, and A5895SLW BiMOS II serialinput, latched source drivers are designed for applications emphasizing low output saturation voltages and currents to -250 mA per output. These smart high-side octal, driver ICs merge an 8-bit CMOS shift register, associated CMOS latches, and CMOS control logic (strobe and output enable) with medium current emitter-follower (sourcing) outputs. Typical applications include incandescent or LED displays (both directly driven and multiplexed), non-impact (i.e., thermal) printers, relays, and solenoids. Each device is suitable for high-side applications to -250 mA per channel. The maximum supply voltage is 50 V and a minimum output sustaining voltage rating of 35 V for inductive load applications. Under normal operating conditions, the UCN5895A and UCN5895EP are capable of providing -120 mA (8 outputs continuous and simultaneous) at +65C with a logic supply of 5 V. Similar devices, with higher output current ratings, are the UCN5890A and UCN5891A. BiMOS II devices can operate at greatly improved data-input rates. With a 5 V supply, they will typically operate at better than 5 MHz. At 12 V, significantly higher speeds are obtained. The CMOS inputs provide for minimum loading and are compatible with standard CMOS, PMOS, and NMOS circuits. TTL or DTL circuits may require the use of appropriate pull-up resistors to ensure a proper input-logic high. A CMOS serial data output allows cascading these devices in multiple drive-line applications required by many dot matrix, alphanumeric, and bar graph displays. These devices are rated for continuous operation over the temperature range of -20C to +85C. Because of limitations on package power dissipation, the simultaneous operation of all output drivers may require a reduction in duty cycle. The UCN5895A is supplied in a standard 16-pin dual in-line plastic package with a copper lead frame for increased allowable package power dissipation. The UCN5895EP is supplied in a 20-lead plastic leaded chip carrier for minimum area, surface-mount applications. The A5895SLW is supplied in a 16-lead wide-body plastic SOIC.
UCN5895A
GROUND CLOCK SERIAL DATA IN STROBE OUT 1 OUT 2 OUT 3 OUT 4 1 2 3 4 5 6 7 8 ST LATCHES CLK SHIFT REGISTER 16 VDD 15 OE 14 SERIAL DATA OUT LOGIC SUPPLY OUTPUT ENABLE LOAD SUPPLY OUT 8 OUT 7 OUT 6 OUT 5
VBB 13 12 11 10 9
Dwg. PP-026-2A
Note the UCN5895A (DIP) and the A5895SLW (SOIC) are electrically identical and share a common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at TA = +25C
Output Voltage, VOUT . . . . . . . . . . . . . . 50 V Logic Supply Voltage Range, VDD . . . . . . . . . . . . . . . . . . 4.5 V to 12 V Driver Supply Voltage Range, VBB . . . . . . . . . . . . . . . . . . 5.0 V to 50 V Input Voltage Range, VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V Continuous Output Current, IOUT . . . . . . . . . . . . . . . . . . . . . -250 mA Allowable Package Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . See Graph Operating Temperature Range, TA . . . . . . . . . . . . . . . . . -20C to +85C Storage Temperature Range, TS . . . . . . . . . . . . . . . . -55C to +150C
Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static electrical charges.
FEATURES
s s s s s Low Output-Saturation Voltage Source Outputs to 50 V Output Current to -250 mA To 3.3 MHz Data-lnput Rate Low-Power CMOS Logic & Latches
Always order by complete part number, e.g., UCN5895A .
5895 8-BIT SERIAL-INPUT, LATCHED DRIVERS
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
2.5
SUFFIX 'EP', R JA = 59C/W
FUNCTIONAL BLOCK DIAGRAM
CLOCK SERIAL DATA IN 8-BIT SERIAL-PARALLEL SHIFT REGISTER SERIAL DATA OUT
2.0
SUFFIX 'A', R JA = 60C/W
1.5
STROBE GROUND MOS BIPOLAR
LATCHES
VDD
1.0
OUTPUT ENABLE
0.5
SUFFIX 'LW', R JA = 80C/W
VBB
0 25 50 75 100 125 AMBIENT TEMPERATURE IN C 150
OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8
Dwg. GP-024-4
Dwg. No. A-12,654
TYPICAL INPUT CIRCUIT
VDD
IN
UCN5895EP
Dwg. EP-010-4A
TYPICAL OUTPUT DRIVER
Dwg. No. A-14,368
Dwg. No. A-12,655
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 1985, 1999, Allegro MicroSystems, Inc.
5895 8-BIT SERIAL-INPUT, LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25C, VBB = 50 V, VDD = 5 V and 12 V (unless otherwise noted).
Characteristic Output Leakage Current Symbol IOUT TA = +25C TA = +70C Output Saturation Voltage VCE(SAT) IOUT = -60 mA IOUT = -120 mA Output Sustaining Voltage Input Voltage VCE(sus) VIN(1) IOUT = -120 mA, L = 2 mH VDD = 5.0 V VDD = 12 V VIN(0) Input Current IIN(1) VDD = 5 V to 12 V VDD = VIN = 5.0 V VDD = VIN = 12 V Input lmpedance zIN VDD = 5.0 V VDD = 12 V Max. Clock Frequency Serial Data-Output Resistance Turn-ON Delay Turn-OFF Delay Supply Current fCLK rOUT VDD = 5.0 V VDD = 12 V tPLH tPHL IBB Output Enable to Output, IOUT = -120 mA Output Enable to Output, IOUT = -120 mA All outputs ON, All outputs open All outputs OFF IDD VDD = 5 V, All outputs OFF, Inputs = 0 V VDD = 12 V, All outputs OFF, Inputs = 0 V VDD = 5 V, One output ON, All inputs = 0 V VDD = 12 V, One output ON, All inputs = 0 V Diode Leakage Current IR VR = 25 V, TA = +25C VR = 25 V, TA = +70C Diode Forward Voltage VF IF = 120 mA Test Conditions Min. -- -- -- -- 35 3.5 10.5 -0.3 -- -- 100 50 3.3 -- -- -- -- -- -- -- -- -- -- -- -- -- Limits Max. -50 -100 1.1 1.2 -- 5.3 12.3 +0.8 50 240 -- -- -- 20 6.0 2.0 10 10 200 100 200 1.0 3.0 50 100 2.0 Units A A V V V V V V A A k k MHz k k s s mA A A A mA mA A A V
5895 8-BIT SERIAL-INPUT, LATCHED DRIVERS
CLOCK DATA IN
A
B
D
E C
F
STROBE BLANKING G OUTN
Dwg. No. A-12,649A
TIMING CONDITIONS
(VDD = 5.0 V, Logic Levels are VDD and Ground)
A. B. C. D. E. F. G. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time) ................................................................. 75 ns Minimum Data Active Time After Clock Pulse (Data Hold Time) ..................................................................... 75 ns Minimum Data Pulse Width ........................................................ 150 ns Minimum Clock Pulse Width ...................................................... 150 ns Minimum Time Between Clock Activation and Strobe ............... 300 ns Minimum Strobe Pulse Width ..................................................... 100 ns Typical Time Between Strobe Activation and Output Transition .................................................................... 1.0 s
Serial Data present at the input is transferred to the shift register on the logic "0" to logic "1" transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the OUTPUT ENABLE input be high during serial data entry. When the OUTPUT ENABLE input is high, all of the output buffers are disabled (OFF) without affecting the information stored in the latches or shift register. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5895 8-BIT SERIAL-INPUT, LATCHED DRIVERS
TYPICAL APPLICATION
+ 12 V
UCN5895A
1
CLOCK
16
SHIFT REGISTER
VDD
OE
DATA OUT FOR > 8 SEGMENTS PER DIGIT
2 3 4 5 6 7 8
15 14 13 12 11 10 9
OUTPUT ENABLE (ACTIVE LOW)
DATA IN
STROBE
LATCHES
VBB
UCN5821A
CLOCK DATA IN 1C 2 3
SHIFT REGISTER LATCHES
TO OTHER SEGMENTS 16 15 14 13 12 11 10 9 9 TO OTHER DIGITS
+ 12 V DATA OUT STROBE OUTPUT ENABLE
4 5 6 7 8
Dwg. No. B-1541
TRUTH TABLE
Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN H L X H L X R1 R2 ... R1 R2 ... X X ... RN-2 RN-1 RN-2 RN-1 RN-1 RN X X PN-1 PN Serial Data Strobe Output Input RN-1 RN-1 RN X PN L H R1 R2 R3 ... P1 P2 P3 ... X
L = Low Logic Level H = High Logic Level X = Irrelevant
Latch Contents I1 I2 I3 ... IN-1 IN Output Enable
Output Contents I1 I2 I3 ... IN-1 I N
R1 R2 R3 ... P1 P2 P3 ...
RN-1 RN PN-1 PN X X L H P1 P2 P3 ... PN-1 PN L L L ... L L
X
X
...
P = Present State
R = Previous State
5895 8-BIT SERIAL-INPUT, LATCHED DRIVERS
UCN5895A
Dimensions in Inches
(controlling dimensions)
16 9 0.014 0.008
0.430 0.280 0.240
MAX
0.300
BSC
1 0.070 0.045
0.100 0.775 0.735
BSC
8 0.005
MIN
0.210
MAX
0.015
MIN
0.150 0.115 0.022 0.014
Dwg. MA-001-16A in
Dimensions in Millimeters
(for reference only)
16 9 0.355 0.204
10.92 7.11 6.10
MAX
7.62
BSC
1 1.77 1.15
2.54 19.68 18.67
BSC
8 0.13
MIN
5.33
MAX
0.39
MIN
3.81 2.93 0.558 0.356
Dwg. MA-001-16A mm
NOTES: 1. Lead thickness is measured at seating plane or below. 2. Lead spacing tolerance is non-cumulative. 3. Exact body and lead configuration at vendor's option within limits shown.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5895 8-BIT SERIAL-INPUT, LATCHED DRIVERS
UCN5895EP
Dimensions in Inches
(controlling dimensions)
13 0.021 0.013 0.169 0.141 14 0.395 0.385 0.032 0.026
INDEX AREA
9
8
0.050 0.169 0.141
BSC
0.356 0.350 18 4
19 0.020
MIN
20
1
2
3
0.356 0.350 0.395 0.385
Dwg. MA-005-20A in
0.180 0.165
Dimensions in Millimeters
(for reference only)
13 0.533 0.331 4.29 3.58 14 10.03 9.78 0.812 0.661
INDEX AREA
9
8
1.27 4.29 3.58
BSC
9.042 8.890 18 4
19 0.51
MIN
20
1
2
3
9.042 8.890 10.03 9.78
Dwg. MA-005-20A mm
4.57 4.20
NOTES: 1. Lead spacing tolerance is non-cumulative. 2. Exact body and lead configuration at vendor's option within limits shown.
5895 8-BIT SERIAL-INPUT, LATCHED DRIVERS
A5895SLW
Dimensions in Inches
(for reference only)
16 9 0.0125 0.0091
0.2992 0.2914
0.419 0.394
0.050 0.016 0.020 0.013
1
2
3 0.4133 0.3977
0.050
BSC
0 TO 8
0.0926 0.1043 0.0040 MIN.
Dwg. MA-008-16A in
Dimensions in Millimeters
(controlling dimensions)
16 9 0.32 0.23
7.60 7.40
10.65 10.00
1.27 0.40 0.51 0.33
1
2
3 10.50 10.10
1.27
BSC
0 TO 8
2.65 2.35 0.10 MIN.
NOTES: 1. Lead spacing tolerance is non-cumulative. 2. Exact body and lead configuration at vendor's option within limits shown.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the designMA-008-16A mm Dwg. of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

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